Simulation and Verification of Vhdl Design of 32-bit Fpau in Simulink

The HDL Code Generation step in MATLAB generates HDL code from the fixed-point Matlab code. One can generate either VHDL or Verilog code that implements the Matlab design. In addition to generating synthesizable HDL code, HDL CoderTM also generates various reports, including a traceability report that helps to navigate between the Matlab code and the generated HDL code. It also shows resource utilization report at the algorithm level, approximately what hardware resources are needed to implement the design, in terms of adders, multipliers, and RAMs [Simulink HDL Coder User’s Guide (2006-2010)]. In the recent, Abdullah and Hadi (2010), Mishra, Save and Rane (2011) and Valenzuela and Abdullah (2011) have used the graphical Matlab/Simulink environment for FPGA emulation, ASIC design, verification and chip testing. In the work carried out on VHDL code generation with Matlab /Simulink, there is hardly any reference of work in the literature for linking the VHDL design system on to the Matlab/simulink. Once the link between Modelsim and Matlab/simulink is created and the VHDL design is up-loading on to the simulink the same then can be optimized to get the optimal results in respect of power, area and speed.